Descripción de Contador de 4bits en VHDL
LIBRARY IEEE; USE IEEE.STD_logic_1164.all; ENTITY CONTADOR09 IS PORT(CLK, RST: IN STD_LOGIC; CUENTA: OUT INTEGER RANGE 0 TO 15); END ENTITY; ARCHITECTURE ALGO OF CONTADOR09 IS SIGNAL AUX: INTEGER RANGE 0 TO 15; BEGIN PROCESS(CLK,RST) BEGIN IF RST='0' THEN AUX<=0; ELSE IF CLK'EVENT AND CLK='0' THEN AUX<=AUX+1; END IF; END IF; END PROCESS; CUENTA<=AUX; END ALGO;