Algo de VHDL

Saludos, les traigo un código de VHDL, es la descripción de un FF tipo D


----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FF is
    Port ( D,CLK: in  STD_LOGIC;
    Q : out  STD_LOGIC);
end FF; 

architecture Behavioral of FF is

  begin--Architecture
  process(CLK)
  begin --Process
  
  IF CLK'EVENT AND CLK='0' THEN Q<=D;
  END IF;
  
  end process;  -- Process


end Behavioral;--architecture